1. Field of the Invention
The present invention relates to multibank memory devices and, more particularly, relates to an improved bank interlock scheme and test mode for multibank memory devices.
2. Description of the Prior Art
It is known that the entire memory array in a multibank memory device is divided into functionally identical memory banks. Each bank typically has the same number of word lines and bit lines which may be activated independent of each other bank. As a result, the row address used to activate one bank need not be the same as any other row address used to activate any other bank.
It is also known that activation of a word line via a row address results in all memory cells associated with the activated word line being latched in the respective sense amplifiers for each corresponding bit line. In conventional standard operating mode, each read or write command provides bank select information and a column address in order to choose or select a particular bit line of the activated word line of a bank. That is, first the bank select information is used to select one bank and only in that bank the column address is used to select data out (or write data to) the corresponding sense amplifier. However, because there is only one shared data path, no more than one bank may store data from the associated system write data lines or drive data on the system read data lines.
As a result, testing of the conventional multibank memory device must be performed one bank at a time. While this approach will eventually result in testing of the memory banks, the time to perform such sequential bank-by-bank testing is excessive and, therefore, prohibitive.